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// IP VLNV: xilinx.com:user:instruction_memory:1.0
// IP Revision: 2

(* X_CORE_INFO = "instruction_memory,Vivado 2018.3" *)
(* CHECK_LICENSE_TYPE = "design_1_instruction_memory_0_0,instruction_memory,{}" *)
(* CORE_GENERATION_INFO = "design_1_instruction_memory_0_0,instruction_memory,{x_ipProduct=Vivado 2018.3,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=instruction_memory,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,INS0=0x00620820,INS1=0x00853021,INS2=0x00212024,INS3=0x00212825,INS4=0x20290064}" *)
(* IP_DEFINITION_SOURCE = "package_project" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_instruction_memory_0_0 (
  op,
  rs,
  rt,
  rd,
  func,
  sign_extend,
  pc_addr,
  clk
);

output wire [5 : 0] op;
output wire [4 : 0] rs;
output wire [4 : 0] rt;
output wire [4 : 0] rd;
output wire [5 : 0] func;
output wire [15 : 0] sign_extend;
input wire [4 : 0] pc_addr;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_clk_0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;

  instruction_memory #(
    .INS0('H00620820),
    .INS1('H00853021),
    .INS2('H00212024),
    .INS3('H00212825),
    .INS4('H20290064)
  ) inst (
    .op(op),
    .rs(rs),
    .rt(rt),
    .rd(rd),
    .func(func),
    .sign_extend(sign_extend),
    .pc_addr(pc_addr),
    .clk(clk)
  );
endmodule
